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    <h1>File: /Users/paulross/dev/linux/linux-3.13/arch/x86/include/asm/cpufeature.h</h1>
    <p>Green shading in the line number column
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    <pre><a name="1" /><span class="True">       1:</span> <span class="k">/*</span>
<a name="2" /><span class="True">       2:</span> <span class="k"> * Defines x86 CPU feature bits</span>
<a name="3" /><span class="True">       3:</span> <span class="k"> */</span>
<a name="4" /><span class="Maybe">       4:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_ref.html#_X0FTTV9YODZfQ1BVRkVBVFVSRV9IXzA_"><span class="b">_ASM_X86_CPUFEATURE_H</span></a>
<a name="5" /><span class="Maybe">       5:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_X0FTTV9YODZfQ1BVRkVBVFVSRV9IXzA_"><span class="b">_ASM_X86_CPUFEATURE_H</span></a>
<a name="6" /><span class="Maybe">       6:</span> 
<a name="7" /><span class="Maybe">       7:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_ref.html#_X0FTTV9YODZfUkVRVUlSRURfRkVBVFVSRVNfSF8w"><span class="b">_ASM_X86_REQUIRED_FEATURES_H</span></a>
<a name="8" /><span class="Maybe">       8:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="m">asm</span><span class="f">/</span><span class="b">required</span><span class="f">-</span><span class="b">features</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="9" /><span class="Maybe">       9:</span> <span class="f">#</span><span class="n">endif</span>
<a name="10" /><span class="Maybe">      10:</span> 
<a name="11" /><span class="Maybe">      11:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TkNBUElOVFNfMA__"><span class="b">NCAPINTS</span></a>    <span class="c">10</span>    <span class="k">/* N 32-bit words worth of info */</span>
<a name="12" /><span class="Maybe">      12:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TkJVR0lOVFNfMA__"><span class="b">NBUGINTS</span></a>    <span class="c">1</span>    <span class="k">/* N 32-bit bug flags */</span>
<a name="13" /><span class="Maybe">      13:</span> 
<a name="14" /><span class="Maybe">      14:</span> <span class="k">/*</span>
<a name="15" /><span class="Maybe">      15:</span> <span class="k"> * Note: If the comment begins with a quoted string, that string is used</span>
<a name="16" /><span class="Maybe">      16:</span> <span class="k"> * in /proc/cpuinfo instead of the macro name.  If the string is &quot;&quot;,</span>
<a name="17" /><span class="Maybe">      17:</span> <span class="k"> * this feature bit is not displayed in /proc/cpuinfo at all.</span>
<a name="18" /><span class="Maybe">      18:</span> <span class="k"> */</span>
<a name="19" /><span class="Maybe">      19:</span> 
<a name="20" /><span class="Maybe">      20:</span> <span class="k">/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */</span>
<a name="21" /><span class="Maybe">      21:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRlBVXzA_"><span class="b">X86_FEATURE_FPU</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* Onboard FPU */</span>
<a name="22" /><span class="Maybe">      22:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVk1FXzA_"><span class="b">X86_FEATURE_VME</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* Virtual Mode Extensions */</span>
<a name="23" /><span class="Maybe">      23:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfREVfMA__"><span class="b">X86_FEATURE_DE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* Debugging Extensions */</span>
<a name="24" /><span class="Maybe">      24:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUFNFXzA_"><span class="b">X86_FEATURE_PSE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* Page Size Extensions */</span>
<a name="25" /><span class="Maybe">      25:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDXzA_"><span class="b">X86_FEATURE_TSC</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* Time Stamp Counter */</span>
<a name="26" /><span class="Maybe">      26:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTVNSXzA_"><span class="b">X86_FEATURE_MSR</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* Model-Specific Registers */</span>
<a name="27" /><span class="Maybe">      27:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUEFFXzA_"><span class="b">X86_FEATURE_PAE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* Physical Address Extensions */</span>
<a name="28" /><span class="Maybe">      28:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTUNFXzA_"><span class="b">X86_FEATURE_MCE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* Machine Check Exception */</span>
<a name="29" /><span class="Maybe">      29:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQ1g4XzA_"><span class="b">X86_FEATURE_CX8</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* CMPXCHG8 instruction */</span>
<a name="30" /><span class="Maybe">      30:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVBJQ18w"><span class="b">X86_FEATURE_APIC</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* Onboard APIC */</span>
<a name="31" /><span class="Maybe">      31:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU0VQXzA_"><span class="b">X86_FEATURE_SEP</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* SYSENTER/SYSEXIT */</span>
<a name="32" /><span class="Maybe">      32:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTVRSUl8w"><span class="b">X86_FEATURE_MTRR</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* Memory Type Range Registers */</span>
<a name="33" /><span class="Maybe">      33:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUEdFXzA_"><span class="b">X86_FEATURE_PGE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* Page Global Enable */</span>
<a name="34" /><span class="Maybe">      34:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTUNBXzA_"><span class="b">X86_FEATURE_MCA</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">14</span><span class="f">)</span> <span class="k">/* Machine Check Architecture */</span>
<a name="35" /><span class="Maybe">      35:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQ01PVl8w"><span class="b">X86_FEATURE_CMOV</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">15</span><span class="f">)</span> <span class="k">/* CMOV instructions */</span>
<a name="36" /><span class="Maybe">      36:</span>                       <span class="k">/* (plus FCMOVcc, FCOMI with FPU) */</span>
<a name="37" /><span class="Maybe">      37:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEFUXzA_"><span class="b">X86_FEATURE_PAT</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">16</span><span class="f">)</span> <span class="k">/* Page Attribute Table */</span>
<a name="38" /><span class="Maybe">      38:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUFNFMzZfMA__"><span class="b">X86_FEATURE_PSE36</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">17</span><span class="f">)</span> <span class="k">/* 36-bit PSEs */</span>
<a name="39" /><span class="Maybe">      39:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUE5fMA__"><span class="b">X86_FEATURE_PN</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">18</span><span class="f">)</span> <span class="k">/* Processor serial number */</span>
<a name="40" /><span class="Maybe">      40:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0xGTFNIXzA_"><span class="b">X86_FEATURE_CLFLSH</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* &quot;clflush&quot; CLFLUSH instruction */</span>
<a name="41" /><span class="Maybe">      41:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRFNfMA__"><span class="b">X86_FEATURE_DS</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">21</span><span class="f">)</span> <span class="k">/* &quot;dts&quot; Debug Store */</span>
<a name="42" /><span class="Maybe">      42:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQUNQSV8w"><span class="b">X86_FEATURE_ACPI</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">22</span><span class="f">)</span> <span class="k">/* ACPI via MSR */</span>
<a name="43" /><span class="Maybe">      43:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTU1YXzA_"><span class="b">X86_FEATURE_MMX</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">23</span><span class="f">)</span> <span class="k">/* Multimedia Extensions */</span>
<a name="44" /><span class="Maybe">      44:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRlhTUl8w"><span class="b">X86_FEATURE_FXSR</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">24</span><span class="f">)</span> <span class="k">/* FXSAVE/FXRSTOR, CR4.OSFXSR */</span>
<a name="45" /><span class="Maybe">      45:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NXzA_"><span class="b">X86_FEATURE_XMM</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">25</span><span class="f">)</span> <span class="k">/* &quot;sse&quot; */</span>
<a name="46" /><span class="Maybe">      46:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NMl8w"><span class="b">X86_FEATURE_XMM2</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">26</span><span class="f">)</span> <span class="k">/* &quot;sse2&quot; */</span>
<a name="47" /><span class="Maybe">      47:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU0VMRlNOT09QXzA_"><span class="b">X86_FEATURE_SELFSNOOP</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">27</span><span class="f">)</span> <span class="k">/* &quot;ss&quot; CPU self snoop */</span>
<a name="48" /><span class="Maybe">      48:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfSFRfMA__"><span class="b">X86_FEATURE_HT</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">28</span><span class="f">)</span> <span class="k">/* Hyper-Threading */</span>
<a name="49" /><span class="Maybe">      49:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUNDXzA_"><span class="b">X86_FEATURE_ACC</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">29</span><span class="f">)</span> <span class="k">/* &quot;tm&quot; Automatic clock control */</span>
<a name="50" /><span class="Maybe">      50:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSUE2NF8w"><span class="b">X86_FEATURE_IA64</span></a>    <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">30</span><span class="f">)</span> <span class="k">/* IA-64 processor */</span>
<a name="51" /><span class="Maybe">      51:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEJFXzA_"><span class="b">X86_FEATURE_PBE</span></a>        <span class="f">(</span><span class="c">0</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">31</span><span class="f">)</span> <span class="k">/* Pending Break Enable */</span>
<a name="52" /><span class="Maybe">      52:</span> 
<a name="53" /><span class="Maybe">      53:</span> <span class="k">/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */</span>
<a name="54" /><span class="Maybe">      54:</span> <span class="k">/* Don&apos;t duplicate feature flags which are redundant with Intel! */</span>
<a name="55" /><span class="Maybe">      55:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1lTQ0FMTF8w"><span class="b">X86_FEATURE_SYSCALL</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* SYSCALL/SYSRET */</span>
<a name="56" /><span class="Maybe">      56:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTVBfMA__"><span class="b">X86_FEATURE_MP</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* MP Capable. */</span>
<a name="57" /><span class="Maybe">      57:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTlhfMA__"><span class="b">X86_FEATURE_NX</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">20</span><span class="f">)</span> <span class="k">/* Execute Disable */</span>
<a name="58" /><span class="Maybe">      58:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTU1YRVhUXzA_"><span class="b">X86_FEATURE_MMXEXT</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">22</span><span class="f">)</span> <span class="k">/* AMD MMX extensions */</span>
<a name="59" /><span class="Maybe">      59:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRlhTUl9PUFRfMA__"><span class="b">X86_FEATURE_FXSR_OPT</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">25</span><span class="f">)</span> <span class="k">/* FXSAVE/FXRSTOR optimizations */</span>
<a name="60" /><span class="Maybe">      60:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfR0JQQUdFU18w"><span class="b">X86_FEATURE_GBPAGES</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">26</span><span class="f">)</span> <span class="k">/* &quot;pdpe1gb&quot; GB pages */</span>
<a name="61" /><span class="Maybe">      61:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUkRUU0NQXzA_"><span class="b">X86_FEATURE_RDTSCP</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">27</span><span class="f">)</span> <span class="k">/* RDTSCP */</span>
<a name="62" /><span class="Maybe">      62:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTE1fMA__"><span class="b">X86_FEATURE_LM</span></a>        <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">29</span><span class="f">)</span> <span class="k">/* Long Mode (x86-64) */</span>
<a name="63" /><span class="Maybe">      63:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfM0ROT1dFWFRfMA__"><span class="b">X86_FEATURE_3DNOWEXT</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">30</span><span class="f">)</span> <span class="k">/* AMD 3DNow! extensions */</span>
<a name="64" /><span class="Maybe">      64:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfM0ROT1dfMA__"><span class="b">X86_FEATURE_3DNOW</span></a>    <span class="f">(</span><span class="c">1</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">31</span><span class="f">)</span> <span class="k">/* 3DNow! */</span>
<a name="65" /><span class="Maybe">      65:</span> 
<a name="66" /><span class="Maybe">      66:</span> <span class="k">/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */</span>
<a name="67" /><span class="Maybe">      67:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUkVDT1ZFUllfMA__"><span class="b">X86_FEATURE_RECOVERY</span></a>    <span class="f">(</span><span class="c">2</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* CPU in recovery mode */</span>
<a name="68" /><span class="Maybe">      68:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTE9OR1JVTl8w"><span class="b">X86_FEATURE_LONGRUN</span></a>    <span class="f">(</span><span class="c">2</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* Longrun power control */</span>
<a name="69" /><span class="Maybe">      69:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTFJUSV8w"><span class="b">X86_FEATURE_LRTI</span></a>    <span class="f">(</span><span class="c">2</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* LongRun table interface */</span>
<a name="70" /><span class="Maybe">      70:</span> 
<a name="71" /><span class="Maybe">      71:</span> <span class="k">/* Other features, Linux-defined mapping, word 3 */</span>
<a name="72" /><span class="Maybe">      72:</span> <span class="k">/* This range is used for feature bits which conflict or are synthesized */</span>
<a name="73" /><span class="Maybe">      73:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1hNTVhfMA__"><span class="b">X86_FEATURE_CXMMX</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* Cyrix MMX extensions */</span>
<a name="74" /><span class="Maybe">      74:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSzZfTVRSUl8w"><span class="b">X86_FEATURE_K6_MTRR</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* AMD K6 nonstandard MTRRs */</span>
<a name="75" /><span class="Maybe">      75:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1lSSVhfQVJSXzA_"><span class="b">X86_FEATURE_CYRIX_ARR</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* Cyrix ARRs (= MTRRs) */</span>
<a name="76" /><span class="Maybe">      76:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0VOVEFVUl9NQ1JfMA__"><span class="b">X86_FEATURE_CENTAUR_MCR</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* Centaur MCRs (= MTRRs) */</span>
<a name="77" /><span class="Maybe">      77:</span> <span class="k">/* cpu types for specific tunings: */</span>
<a name="78" /><span class="Maybe">      78:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSzhfMA__"><span class="b">X86_FEATURE_K8</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* &quot;&quot; Opteron, Athlon64 */</span>
<a name="79" /><span class="Maybe">      79:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSzdfMA__"><span class="b">X86_FEATURE_K7</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* &quot;&quot; Athlon */</span>
<a name="80" /><span class="Maybe">      80:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUDNfMA__"><span class="b">X86_FEATURE_P3</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* &quot;&quot; P3 */</span>
<a name="81" /><span class="Maybe">      81:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUDRfMA__"><span class="b">X86_FEATURE_P4</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* &quot;&quot; P4 */</span>
<a name="82" /><span class="Maybe">      82:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ09OU1RBTlRfVFNDXzA_"><span class="b">X86_FEATURE_CONSTANT_TSC</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* TSC ticks at a constant rate */</span>
<a name="83" /><span class="Maybe">      83:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVVBfMA__"><span class="b">X86_FEATURE_UP</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* smp kernel running on up */</span>
<a name="84" /><span class="Maybe">      84:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRlhTQVZFX0xFQUtfMA__"><span class="b">X86_FEATURE_FXSAVE_LEAK</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* &quot;&quot; FXSAVE leaks FOP/FIP/FOP */</span>
<a name="85" /><span class="Maybe">      85:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVJDSF9QRVJGTU9OXzA_"><span class="b">X86_FEATURE_ARCH_PERFMON</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* Intel Architectural PerfMon */</span>
<a name="86" /><span class="Maybe">      86:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVCU18w"><span class="b">X86_FEATURE_PEBS</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* Precise-Event Based Sampling */</span>
<a name="87" /><span class="Maybe">      87:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQlRTXzA_"><span class="b">X86_FEATURE_BTS</span></a>        <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* Branch Trace Store */</span>
<a name="88" /><span class="Maybe">      88:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1lTQ0FMTDMyXzA_"><span class="b">X86_FEATURE_SYSCALL32</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">14</span><span class="f">)</span> <span class="k">/* &quot;&quot; syscall in ia32 userspace */</span>
<a name="89" /><span class="Maybe">      89:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1lTRU5URVIzMl8w"><span class="b">X86_FEATURE_SYSENTER32</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">15</span><span class="f">)</span> <span class="k">/* &quot;&quot; sysenter in ia32 userspace */</span>
<a name="90" /><span class="Maybe">      90:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUkVQX0dPT0RfMA__"><span class="b">X86_FEATURE_REP_GOOD</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">16</span><span class="f">)</span> <span class="k">/* rep microcode works well */</span>
<a name="91" /><span class="Maybe">      91:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTUZFTkNFX1JEVFNDXzA_"><span class="b">X86_FEATURE_MFENCE_RDTSC</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">17</span><span class="f">)</span> <span class="k">/* &quot;&quot; Mfence synchronizes RDTSC */</span>
<a name="92" /><span class="Maybe">      92:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTEZFTkNFX1JEVFNDXzA_"><span class="b">X86_FEATURE_LFENCE_RDTSC</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">18</span><span class="f">)</span> <span class="k">/* &quot;&quot; Lfence synchronizes RDTSC */</span>
<a name="93" /><span class="Maybe">      93:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfMTFBUF8w"><span class="b">X86_FEATURE_11AP</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* &quot;&quot; Bad local APIC aka 11AP */</span>
<a name="94" /><span class="Maybe">      94:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTk9QTF8w"><span class="b">X86_FEATURE_NOPL</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">20</span><span class="f">)</span> <span class="k">/* The NOPL (0F 1F) instructions */</span>
<a name="95" /><span class="Maybe">      95:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQUxXQVlTXzA_"><span class="b">X86_FEATURE_ALWAYS</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">21</span><span class="f">)</span> <span class="k">/* &quot;&quot; Always-present feature */</span>
<a name="96" /><span class="Maybe">      96:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFRPUE9MT0dZXzA_"><span class="b">X86_FEATURE_XTOPOLOGY</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">22</span><span class="f">)</span> <span class="k">/* cpu topology enum extensions */</span>
<a name="97" /><span class="Maybe">      97:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDX1JFTElBQkxFXzA_"><span class="b">X86_FEATURE_TSC_RELIABLE</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">23</span><span class="f">)</span> <span class="k">/* TSC is known to be reliable */</span>
<a name="98" /><span class="Maybe">      98:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTk9OU1RPUF9UU0NfMA__"><span class="b">X86_FEATURE_NONSTOP_TSC</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">24</span><span class="f">)</span> <span class="k">/* TSC does not stop in C states */</span>
<a name="99" /><span class="Maybe">      99:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0xGTFVTSF9NT05JVE9SXzA_"><span class="b">X86_FEATURE_CLFLUSH_MONITOR</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">25</span><span class="f">)</span> <span class="k">/* &quot;&quot; clflush reqd with monitor */</span>
<a name="100" /><span class="Maybe">     100:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRVhURF9BUElDSURfMA__"><span class="b">X86_FEATURE_EXTD_APICID</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">26</span><span class="f">)</span> <span class="k">/* has extended APICID (8 bits) */</span>
<a name="101" /><span class="Maybe">     101:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQU1EX0RDTV8w"><span class="b">X86_FEATURE_AMD_DCM</span></a>     <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">27</span><span class="f">)</span> <span class="k">/* multi-node processor */</span>
<a name="102" /><span class="Maybe">     102:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVBFUkZNUEVSRl8w"><span class="b">X86_FEATURE_APERFMPERF</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">28</span><span class="f">)</span> <span class="k">/* APERFMPERF */</span>
<a name="103" /><span class="Maybe">     103:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRUFHRVJfRlBVXzA_"><span class="b">X86_FEATURE_EAGER_FPU</span></a>    <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">29</span><span class="f">)</span> <span class="k">/* &quot;eagerfpu&quot; Non lazy FPU restore */</span>
<a name="104" /><span class="Maybe">     104:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTk9OU1RPUF9UU0NfUzNfMA__"><span class="b">X86_FEATURE_NONSTOP_TSC_S3</span></a> <span class="f">(</span><span class="c">3</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">30</span><span class="f">)</span> <span class="k">/* TSC doesn&apos;t stop in S3 state */</span>
<a name="105" /><span class="Maybe">     105:</span> 
<a name="106" /><span class="Maybe">     106:</span> <span class="k">/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */</span>
<a name="107" /><span class="Maybe">     107:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NM18w"><span class="b">X86_FEATURE_XMM3</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* &quot;pni&quot; SSE-3 */</span>
<a name="108" /><span class="Maybe">     108:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUENMTVVMUURRXzA_"><span class="b">X86_FEATURE_PCLMULQDQ</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* PCLMULQDQ instruction */</span>
<a name="109" /><span class="Maybe">     109:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRFRFUzY0XzA_"><span class="b">X86_FEATURE_DTES64</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* 64-bit Debug Store */</span>
<a name="110" /><span class="Maybe">     110:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfTVdBSVRfMA__"><span class="b">X86_FEATURE_MWAIT</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* &quot;monitor&quot; Monitor/Mwait support */</span>
<a name="111" /><span class="Maybe">     111:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRFNDUExfMA__"><span class="b">X86_FEATURE_DSCPL</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* &quot;ds_cpl&quot; CPL Qual. Debug Store */</span>
<a name="112" /><span class="Maybe">     112:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVk1YXzA_"><span class="b">X86_FEATURE_VMX</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* Hardware virtualization */</span>
<a name="113" /><span class="Maybe">     113:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU01YXzA_"><span class="b">X86_FEATURE_SMX</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* Safer mode */</span>
<a name="114" /><span class="Maybe">     114:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRVNUXzA_"><span class="b">X86_FEATURE_EST</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* Enhanced SpeedStep */</span>
<a name="115" /><span class="Maybe">     115:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVE0yXzA_"><span class="b">X86_FEATURE_TM2</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* Thermal Monitor 2 */</span>
<a name="116" /><span class="Maybe">     116:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1NTRTNfMA__"><span class="b">X86_FEATURE_SSSE3</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* Supplemental SSE-3 */</span>
<a name="117" /><span class="Maybe">     117:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0lEXzA_"><span class="b">X86_FEATURE_CID</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* Context ID */</span>
<a name="118" /><span class="Maybe">     118:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRk1BXzA_"><span class="b">X86_FEATURE_FMA</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* Fused multiply-add */</span>
<a name="119" /><span class="Maybe">     119:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1gxNl8w"><span class="b">X86_FEATURE_CX16</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* CMPXCHG16B */</span>
<a name="120" /><span class="Maybe">     120:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFRQUl8w"><span class="b">X86_FEATURE_XTPR</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">14</span><span class="f">)</span> <span class="k">/* Send Task Priority Messages */</span>
<a name="121" /><span class="Maybe">     121:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUERDTV8w"><span class="b">X86_FEATURE_PDCM</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">15</span><span class="f">)</span> <span class="k">/* Performance Capabilities */</span>
<a name="122" /><span class="Maybe">     122:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUENJRF8w"><span class="b">X86_FEATURE_PCID</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">17</span><span class="f">)</span> <span class="k">/* Process Context Identifiers */</span>
<a name="123" /><span class="Maybe">     123:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRENBXzA_"><span class="b">X86_FEATURE_DCA</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">18</span><span class="f">)</span> <span class="k">/* Direct Cache Access */</span>
<a name="124" /><span class="Maybe">     124:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NNF8xXzA_"><span class="b">X86_FEATURE_XMM4_1</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* &quot;sse4_1&quot; SSE-4.1 */</span>
<a name="125" /><span class="Maybe">     125:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NNF8yXzA_"><span class="b">X86_FEATURE_XMM4_2</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">20</span><span class="f">)</span> <span class="k">/* &quot;sse4_2&quot; SSE-4.2 */</span>
<a name="126" /><span class="Maybe">     126:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWDJBUElDXzA_"><span class="b">X86_FEATURE_X2APIC</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">21</span><span class="f">)</span> <span class="k">/* x2APIC */</span>
<a name="127" /><span class="Maybe">     127:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTU9WQkVfMA__"><span class="b">X86_FEATURE_MOVBE</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">22</span><span class="f">)</span> <span class="k">/* MOVBE instruction */</span>
<a name="128" /><span class="Maybe">     128:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUE9QQ05UXzA_"><span class="b">X86_FEATURE_POPCNT</span></a>      <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">23</span><span class="f">)</span> <span class="k">/* POPCNT instruction */</span>
<a name="129" /><span class="Maybe">     129:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDX0RFQURMSU5FX1RJTUVSXzA_"><span class="b">X86_FEATURE_TSC_DEADLINE_TIMER</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">24</span><span class="f">)</span> <span class="k">/* Tsc deadline timer */</span>
<a name="130" /><span class="Maybe">     130:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUVTXzA_"><span class="b">X86_FEATURE_AES</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">25</span><span class="f">)</span> <span class="k">/* AES instructions */</span>
<a name="131" /><span class="Maybe">     131:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNBVkVfMA__"><span class="b">X86_FEATURE_XSAVE</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">26</span><span class="f">)</span> <span class="k">/* XSAVE/XRSTOR/XSETBV/XGETBV */</span>
<a name="132" /><span class="Maybe">     132:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfT1NYU0FWRV8w"><span class="b">X86_FEATURE_OSXSAVE</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">27</span><span class="f">)</span> <span class="k">/* &quot;&quot; XSAVE enabled in the OS */</span>
<a name="133" /><span class="Maybe">     133:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVZYXzA_"><span class="b">X86_FEATURE_AVX</span></a>        <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">28</span><span class="f">)</span> <span class="k">/* Advanced Vector Extensions */</span>
<a name="134" /><span class="Maybe">     134:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRjE2Q18w"><span class="b">X86_FEATURE_F16C</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">29</span><span class="f">)</span> <span class="k">/* 16-bit fp conversions */</span>
<a name="135" /><span class="Maybe">     135:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUkRSQU5EXzA_"><span class="b">X86_FEATURE_RDRAND</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">30</span><span class="f">)</span> <span class="k">/* The RDRAND instruction */</span>
<a name="136" /><span class="Maybe">     136:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSFlQRVJWSVNPUl8w"><span class="b">X86_FEATURE_HYPERVISOR</span></a>    <span class="f">(</span><span class="c">4</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">31</span><span class="f">)</span> <span class="k">/* Running on a hypervisor */</span>
<a name="137" /><span class="Maybe">     137:</span> 
<a name="138" /><span class="Maybe">     138:</span> <span class="k">/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */</span>
<a name="139" /><span class="Maybe">     139:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNUT1JFXzA_"><span class="b">X86_FEATURE_XSTORE</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* &quot;rng&quot; RNG present (xstore) */</span>
<a name="140" /><span class="Maybe">     140:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNUT1JFX0VOXzA_"><span class="b">X86_FEATURE_XSTORE_EN</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* &quot;rng_en&quot; RNG enabled */</span>
<a name="141" /><span class="Maybe">     141:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWENSWVBUXzA_"><span class="b">X86_FEATURE_XCRYPT</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* &quot;ace&quot; on-CPU crypto (xcrypt) */</span>
<a name="142" /><span class="Maybe">     142:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWENSWVBUX0VOXzA_"><span class="b">X86_FEATURE_XCRYPT_EN</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* &quot;ace_en&quot; on-CPU crypto enabled */</span>
<a name="143" /><span class="Maybe">     143:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUNFMl8w"><span class="b">X86_FEATURE_ACE2</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* Advanced Cryptography Engine v2 */</span>
<a name="144" /><span class="Maybe">     144:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUNFMl9FTl8w"><span class="b">X86_FEATURE_ACE2_EN</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* ACE v2 enabled */</span>
<a name="145" /><span class="Maybe">     145:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEhFXzA_"><span class="b">X86_FEATURE_PHE</span></a>        <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* PadLock Hash Engine */</span>
<a name="146" /><span class="Maybe">     146:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEhFX0VOXzA_"><span class="b">X86_FEATURE_PHE_EN</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* PHE enabled */</span>
<a name="147" /><span class="Maybe">     147:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUE1NXzA_"><span class="b">X86_FEATURE_PMM</span></a>        <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* PadLock Montgomery Multiplier */</span>
<a name="148" /><span class="Maybe">     148:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUE1NX0VOXzA_"><span class="b">X86_FEATURE_PMM_EN</span></a>    <span class="f">(</span><span class="c">5</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* PMM enabled */</span>
<a name="149" /><span class="Maybe">     149:</span> 
<a name="150" /><span class="Maybe">     150:</span> <span class="k">/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */</span>
<a name="151" /><span class="Maybe">     151:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTEFIRl9MTV8w"><span class="b">X86_FEATURE_LAHF_LM</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* LAHF/SAHF in long mode */</span>
<a name="152" /><span class="Maybe">     152:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ01QX0xFR0FDWV8w"><span class="b">X86_FEATURE_CMP_LEGACY</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* If yes HyperThreading not valid */</span>
<a name="153" /><span class="Maybe">     153:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1ZNXzA_"><span class="b">X86_FEATURE_SVM</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* Secure virtual machine */</span>
<a name="154" /><span class="Maybe">     154:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRVhUQVBJQ18w"><span class="b">X86_FEATURE_EXTAPIC</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* Extended APIC space */</span>
<a name="155" /><span class="Maybe">     155:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1I4X0xFR0FDWV8w"><span class="b">X86_FEATURE_CR8_LEGACY</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* CR8 in 32-bit mode */</span>
<a name="156" /><span class="Maybe">     156:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUJNXzA_"><span class="b">X86_FEATURE_ABM</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* Advanced bit manipulation */</span>
<a name="157" /><span class="Maybe">     157:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1NFNEFfMA__"><span class="b">X86_FEATURE_SSE4A</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* SSE-4A */</span>
<a name="158" /><span class="Maybe">     158:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTUlTQUxJR05TU0VfMA__"><span class="b">X86_FEATURE_MISALIGNSSE</span></a> <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* Misaligned SSE mode */</span>
<a name="159" /><span class="Maybe">     159:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfM0ROT1dQUkVGRVRDSF8w"><span class="b">X86_FEATURE_3DNOWPREFETCH</span></a> <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* 3DNow prefetch instructions */</span>
<a name="160" /><span class="Maybe">     160:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfT1NWV18w"><span class="b">X86_FEATURE_OSVW</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* OS Visible Workaround */</span>
<a name="161" /><span class="Maybe">     161:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSUJTXzA_"><span class="b">X86_FEATURE_IBS</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* Instruction Based Sampling */</span>
<a name="162" /><span class="Maybe">     162:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE9QXzA_"><span class="b">X86_FEATURE_XOP</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* extended AVX instructions */</span>
<a name="163" /><span class="Maybe">     163:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU0tJTklUXzA_"><span class="b">X86_FEATURE_SKINIT</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* SKINIT/STGI instructions */</span>
<a name="164" /><span class="Maybe">     164:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfV0RUXzA_"><span class="b">X86_FEATURE_WDT</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* Watchdog timer */</span>
<a name="165" /><span class="Maybe">     165:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTFdQXzA_"><span class="b">X86_FEATURE_LWP</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">15</span><span class="f">)</span> <span class="k">/* Light Weight Profiling */</span>
<a name="166" /><span class="Maybe">     166:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRk1BNF8w"><span class="b">X86_FEATURE_FMA4</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">16</span><span class="f">)</span> <span class="k">/* 4 operands MAC instructions */</span>
<a name="167" /><span class="Maybe">     167:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVENFXzA_"><span class="b">X86_FEATURE_TCE</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">17</span><span class="f">)</span> <span class="k">/* translation cache extension */</span>
<a name="168" /><span class="Maybe">     168:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTk9ERUlEX01TUl8w"><span class="b">X86_FEATURE_NODEID_MSR</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* NodeId MSR */</span>
<a name="169" /><span class="Maybe">     169:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVEJNXzA_"><span class="b">X86_FEATURE_TBM</span></a>        <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">21</span><span class="f">)</span> <span class="k">/* trailing bit manipulations */</span>
<a name="170" /><span class="Maybe">     170:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVE9QT0VYVF8w"><span class="b">X86_FEATURE_TOPOEXT</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">22</span><span class="f">)</span> <span class="k">/* topology extensions CPUID leafs */</span>
<a name="171" /><span class="Maybe">     171:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9DT1JFXzA_"><span class="b">X86_FEATURE_PERFCTR_CORE</span></a> <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">23</span><span class="f">)</span> <span class="k">/* core performance counter extensions */</span>
<a name="172" /><span class="Maybe">     172:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9OQl8w"><span class="b">X86_FEATURE_PERFCTR_NB</span></a>  <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">24</span><span class="f">)</span> <span class="k">/* NB performance counter extensions */</span>
<a name="173" /><span class="Maybe">     173:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9MMl8w"><span class="b">X86_FEATURE_PERFCTR_L2</span></a>    <span class="f">(</span><span class="c">6</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">28</span><span class="f">)</span> <span class="k">/* L2 performance counter extensions */</span>
<a name="174" /><span class="Maybe">     174:</span> 
<a name="175" /><span class="Maybe">     175:</span> <span class="k">/*</span>
<a name="176" /><span class="Maybe">     176:</span> <span class="k"> * Auxiliary flags: Linux defined - For features scattered in various</span>
<a name="177" /><span class="Maybe">     177:</span> <span class="k"> * CPUID levels like 0x6, 0xA etc, word 7</span>
<a name="178" /><span class="Maybe">     178:</span> <span class="k"> */</span>
<a name="179" /><span class="Maybe">     179:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSURBXzA_"><span class="b">X86_FEATURE_IDA</span></a>        <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* Intel Dynamic Acceleration */</span>
<a name="180" /><span class="Maybe">     180:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVJBVF8w"><span class="b">X86_FEATURE_ARAT</span></a>    <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* Always Running APIC Timer */</span>
<a name="181" /><span class="Maybe">     181:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1BCXzA_"><span class="b">X86_FEATURE_CPB</span></a>        <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* AMD Core Performance Boost */</span>
<a name="182" /><span class="Maybe">     182:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRVBCXzA_"><span class="b">X86_FEATURE_EPB</span></a>        <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* IA32_ENERGY_PERF_BIAS support */</span>
<a name="183" /><span class="Maybe">     183:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNBVkVPUFRfMA__"><span class="b">X86_FEATURE_XSAVEOPT</span></a>    <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* Optimized Xsave */</span>
<a name="184" /><span class="Maybe">     184:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUExOXzA_"><span class="b">X86_FEATURE_PLN</span></a>        <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* Intel Power Limit Notification */</span>
<a name="185" /><span class="Maybe">     185:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUFRTXzA_"><span class="b">X86_FEATURE_PTS</span></a>        <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* Intel Package Thermal Status */</span>
<a name="186" /><span class="Maybe">     186:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRFRIRVJNXzA_"><span class="b">X86_FEATURE_DTHERM</span></a>    <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* Digital Thermal Sensor */</span>
<a name="187" /><span class="Maybe">     187:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSFdfUFNUQVRFXzA_"><span class="b">X86_FEATURE_HW_PSTATE</span></a>    <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* AMD HW-PState */</span>
<a name="188" /><span class="Maybe">     188:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUFJPQ19GRUVEQkFDS18w"><span class="b">X86_FEATURE_PROC_FEEDBACK</span></a> <span class="f">(</span><span class="c">7</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* AMD ProcFeedbackInterface */</span>
<a name="189" /><span class="Maybe">     189:</span> 
<a name="190" /><span class="Maybe">     190:</span> <span class="k">/* Virtualization flags: Linux defined, word 8 */</span>
<a name="191" /><span class="Maybe">     191:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFBSX1NIQURPV18w"><span class="b">X86_FEATURE_TPR_SHADOW</span></a>  <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* Intel TPR Shadow */</span>
<a name="192" /><span class="Maybe">     192:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVk5NSV8w"><span class="b">X86_FEATURE_VNMI</span></a>        <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* Intel Virtual NMI */</span>
<a name="193" /><span class="Maybe">     193:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRkxFWFBSSU9SSVRZXzA_"><span class="b">X86_FEATURE_FLEXPRIORITY</span></a> <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">2</span><span class="f">)</span> <span class="k">/* Intel FlexPriority */</span>
<a name="194" /><span class="Maybe">     194:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRVBUXzA_"><span class="b">X86_FEATURE_EPT</span></a>         <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* Intel Extended Page Table */</span>
<a name="195" /><span class="Maybe">     195:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVlBJRF8w"><span class="b">X86_FEATURE_VPID</span></a>        <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* Intel Virtual Processor ID */</span>
<a name="196" /><span class="Maybe">     196:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTlBUXzA_"><span class="b">X86_FEATURE_NPT</span></a>        <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* AMD Nested Page Table support */</span>
<a name="197" /><span class="Maybe">     197:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTEJSVl8w"><span class="b">X86_FEATURE_LBRV</span></a>    <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">6</span><span class="f">)</span> <span class="k">/* AMD LBR Virtualization support */</span>
<a name="198" /><span class="Maybe">     198:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1ZNTF8w"><span class="b">X86_FEATURE_SVML</span></a>    <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* &quot;svm_lock&quot; AMD SVM locking MSR */</span>
<a name="199" /><span class="Maybe">     199:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTlJJUFNfMA__"><span class="b">X86_FEATURE_NRIPS</span></a>    <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* &quot;nrip_save&quot; AMD SVM next_rip save */</span>
<a name="200" /><span class="Maybe">     200:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDUkFURU1TUl8w"><span class="b">X86_FEATURE_TSCRATEMSR</span></a>  <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* &quot;tsc_scale&quot; AMD TSC scaling support */</span>
<a name="201" /><span class="Maybe">     201:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVk1DQkNMRUFOXzA_"><span class="b">X86_FEATURE_VMCBCLEAN</span></a>   <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* &quot;vmcb_clean&quot; AMD VMCB clean bits support */</span>
<a name="202" /><span class="Maybe">     202:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRkxVU0hCWUFTSURfMA__"><span class="b">X86_FEATURE_FLUSHBYASID</span></a> <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* AMD flush-by-ASID support */</span>
<a name="203" /><span class="Maybe">     203:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfREVDT0RFQVNTSVNUU18w"><span class="b">X86_FEATURE_DECODEASSISTS</span></a> <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">12</span><span class="f">)</span> <span class="k">/* AMD Decode Assists support */</span>
<a name="204" /><span class="Maybe">     204:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEFVU0VGSUxURVJfMA__"><span class="b">X86_FEATURE_PAUSEFILTER</span></a> <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">13</span><span class="f">)</span> <span class="k">/* AMD filtered pause intercept */</span>
<a name="205" /><span class="Maybe">     205:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEZUSFJFU0hPTERfMA__"><span class="b">X86_FEATURE_PFTHRESHOLD</span></a> <span class="f">(</span><span class="c">8</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">14</span><span class="f">)</span> <span class="k">/* AMD pause filter threshold */</span>
<a name="206" /><span class="Maybe">     206:</span> 
<a name="207" /><span class="Maybe">     207:</span> 
<a name="208" /><span class="Maybe">     208:</span> <span class="k">/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */</span>
<a name="209" /><span class="Maybe">     209:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRlNHU0JBU0VfMA__"><span class="b">X86_FEATURE_FSGSBASE</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">0</span><span class="f">)</span> <span class="k">/* {RD/WR}{FS/GS}BASE instructions*/</span>
<a name="210" /><span class="Maybe">     210:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDX0FESlVTVF8w"><span class="b">X86_FEATURE_TSC_ADJUST</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">1</span><span class="f">)</span> <span class="k">/* TSC adjustment MSR 0x3b */</span>
<a name="211" /><span class="Maybe">     211:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQk1JMV8w"><span class="b">X86_FEATURE_BMI1</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">3</span><span class="f">)</span> <span class="k">/* 1st group bit manipulation extensions */</span>
<a name="212" /><span class="Maybe">     212:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSExFXzA_"><span class="b">X86_FEATURE_HLE</span></a>        <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">4</span><span class="f">)</span> <span class="k">/* Hardware Lock Elision */</span>
<a name="213" /><span class="Maybe">     213:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVZYMl8w"><span class="b">X86_FEATURE_AVX2</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">5</span><span class="f">)</span> <span class="k">/* AVX2 instructions */</span>
<a name="214" /><span class="Maybe">     214:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU01FUF8w"><span class="b">X86_FEATURE_SMEP</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">7</span><span class="f">)</span> <span class="k">/* Supervisor Mode Execution Protection */</span>
<a name="215" /><span class="Maybe">     215:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQk1JMl8w"><span class="b">X86_FEATURE_BMI2</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">8</span><span class="f">)</span> <span class="k">/* 2nd group bit manipulation extensions */</span>
<a name="216" /><span class="Maybe">     216:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRVJNU18w"><span class="b">X86_FEATURE_ERMS</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span> <span class="c">9</span><span class="f">)</span> <span class="k">/* Enhanced REP MOVSB/STOSB */</span>
<a name="217" /><span class="Maybe">     217:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSU5WUENJRF8w"><span class="b">X86_FEATURE_INVPCID</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">10</span><span class="f">)</span> <span class="k">/* Invalidate Processor Context ID */</span>
<a name="218" /><span class="Maybe">     218:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUlRNXzA_"><span class="b">X86_FEATURE_RTM</span></a>        <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">11</span><span class="f">)</span> <span class="k">/* Restricted Transactional Memory */</span>
<a name="219" /><span class="Maybe">     219:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUkRTRUVEXzA_"><span class="b">X86_FEATURE_RDSEED</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">18</span><span class="f">)</span> <span class="k">/* The RDSEED instruction */</span>
<a name="220" /><span class="Maybe">     220:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQURYXzA_"><span class="b">X86_FEATURE_ADX</span></a>        <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">19</span><span class="f">)</span> <span class="k">/* The ADCX and ADOX instructions */</span>
<a name="221" /><span class="Maybe">     221:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfU01BUF8w"><span class="b">X86_FEATURE_SMAP</span></a>    <span class="f">(</span><span class="c">9</span><span class="f">*</span><span class="c">32</span><span class="f">+</span><span class="c">20</span><span class="f">)</span> <span class="k">/* Supervisor Mode Access Prevention */</span>
<a name="222" /><span class="Maybe">     222:</span> 
<a name="223" /><span class="Maybe">     223:</span> <span class="k">/*</span>
<a name="224" /><span class="Maybe">     224:</span> <span class="k"> * BUG word(s)</span>
<a name="225" /><span class="Maybe">     225:</span> <span class="k"> */</span>
<a name="226" /><span class="Maybe">     226:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="b">x</span><span class="f">)</span>        <span class="f">(</span><a href="cpu.c_macros_ref.html#_TkNBUElOVFNfMA__"><span class="b">NCAPINTS</span></a><span class="f">*</span><span class="c">32</span> <span class="f">+</span> <span class="f">(</span><span class="b">x</span><span class="f">)</span><span class="f">)</span>
<a name="227" /><span class="Maybe">     227:</span> 
<a name="228" /><span class="Maybe">     228:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR19GMDBGXzA_"><span class="b">X86_BUG_F00F</span></a>        <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="c">0</span><span class="f">)</span> <span class="k">/* Intel F00F */</span>
<a name="229" /><span class="Maybe">     229:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR19GRElWXzA_"><span class="b">X86_BUG_FDIV</span></a>        <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="c">1</span><span class="f">)</span> <span class="k">/* FPU FDIV */</span>
<a name="230" /><span class="Maybe">     230:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR19DT01BXzA_"><span class="b">X86_BUG_COMA</span></a>        <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="c">2</span><span class="f">)</span> <span class="k">/* Cyrix 6x86 coma */</span>
<a name="231" /><span class="Maybe">     231:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR19BTURfVExCX01NQVRDSF8w"><span class="b">X86_BUG_AMD_TLB_MMATCH</span></a>    <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="c">3</span><span class="f">)</span> <span class="k">/* AMD Erratum 383 */</span>
<a name="232" /><span class="Maybe">     232:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X0JVR19BTURfQVBJQ19DMUVfMA__"><span class="b">X86_BUG_AMD_APIC_C1E</span></a>    <a href="cpu.c_macros_noref.html#_WDg2X0JVR18w"><span class="b">X86_BUG</span></a><span class="f">(</span><span class="c">4</span><span class="f">)</span> <span class="k">/* AMD Erratum 400 */</span>
<a name="233" /><span class="Maybe">     233:</span> 
<a name="234" /><span class="Maybe">     234:</span> <span class="f">#</span><span class="n">if</span> <span class="b">defined</span><span class="f">(</span><a href="cpu.c_macros_ref.html#_X19LRVJORUxfX18w"><span class="b">__KERNEL__</span></a><span class="f">)</span> <span class="f">&amp;&amp;</span> <span class="f">!</span><span class="b">defined</span><span class="f">(</span><span class="b">__ASSEMBLY__</span><span class="f">)</span>
<a name="235" /><span class="Maybe">     235:</span> 
<a name="236" /><span class="Maybe">     236:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="m">asm</span><span class="f">/</span><span class="m">asm</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="237" /><span class="Maybe">     237:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="b">linux</span><span class="f">/</span><span class="b">bitops</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="238" /><span class="Maybe">     238:</span> 
<a name="239" /><span class="Maybe">     239:</span> <span class="m">extern</span> <span class="m">const</span> <span class="m">char</span> <span class="f">*</span> <span class="m">const</span> <span class="b">x86_cap_flags</span><span class="f">[</span><a href="cpu.c_macros_ref.html#_TkNBUElOVFNfMA__"><span class="b">NCAPINTS</span></a><span class="f">*</span><span class="c">32</span><span class="f">]</span><span class="f">;</span>
<a name="240" /><span class="Maybe">     240:</span> <span class="m">extern</span> <span class="m">const</span> <span class="m">char</span> <span class="f">*</span> <span class="m">const</span> <span class="b">x86_power_flags</span><span class="f">[</span><span class="c">32</span><span class="f">]</span><span class="f">;</span>
<a name="241" /><span class="Maybe">     241:</span> 
<a name="242" /><span class="Maybe">     242:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_dGVzdF9jcHVfY2FwXzA_"><span class="b">test_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>                        \
<a name="243" /><span class="Maybe">     243:</span>      <a href="cpu.c_macros_ref.html#_dGVzdF9iaXRfMA__"><span class="b">test_bit</span></a><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="f">(</span><span class="f">(</span><span class="b">c</span><span class="f">)</span><span class="f">-&gt;</span><span class="b">x86_capability</span><span class="f">)</span><span class="f">)</span>
<a name="244" /><span class="Maybe">     244:</span> 
<a name="245" /><span class="Maybe">     245:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTS19CSVRfU0VUXzA_"><span class="b">REQUIRED_MASK_BIT_SET</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>                    \
<a name="246" /><span class="Maybe">     246:</span>      <span class="f">(</span> <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">0</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzBfMA__"><span class="b">REQUIRED_MASK0</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="247" /><span class="Maybe">     247:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">1</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzFfMA__"><span class="b">REQUIRED_MASK1</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="248" /><span class="Maybe">     248:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">2</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzJfMA__"><span class="b">REQUIRED_MASK2</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="249" /><span class="Maybe">     249:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">3</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzNfMA__"><span class="b">REQUIRED_MASK3</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="250" /><span class="Maybe">     250:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">4</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzRfMA__"><span class="b">REQUIRED_MASK4</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="251" /><span class="Maybe">     251:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">5</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzVfMA__"><span class="b">REQUIRED_MASK5</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="252" /><span class="Maybe">     252:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">6</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzZfMA__"><span class="b">REQUIRED_MASK6</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="253" /><span class="Maybe">     253:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">7</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzdfMA__"><span class="b">REQUIRED_MASK7</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="254" /><span class="Maybe">     254:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">8</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzhfMA__"><span class="b">REQUIRED_MASK8</span></a><span class="f">)</span><span class="f">)</span> <span class="f">||</span>    \
<a name="255" /><span class="Maybe">     255:</span>        <span class="f">(</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&gt;&gt;</span><span class="c">5</span><span class="f">)</span><span class="f">==</span><span class="c">9</span> <span class="f">&amp;&amp;</span> <span class="f">(</span><span class="c">1UL</span><span class="f">&lt;&lt;</span><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">&amp;</span><span class="c">31</span><span class="f">)</span> <span class="f">&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTSzlfMA__"><span class="b">REQUIRED_MASK9</span></a><span class="f">)</span><span class="f">)</span> <span class="f">)</span>
<a name="256" /><span class="Maybe">     256:</span> 
<a name="257" /><span class="Maybe">     257:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_Y3B1X2hhc18w"><span class="b">cpu_has</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>                            \
<a name="258" /><span class="Maybe">     258:</span>     <span class="f">(</span><span class="b">__builtin_constant_p</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">&amp;&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTS19CSVRfU0VUXzA_"><span class="b">REQUIRED_MASK_BIT_SET</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">?</span> <span class="c">1</span> <span class="f">:</span>    \
<a name="259" /><span class="Maybe">     259:</span>      <a href="cpu.c_macros_ref.html#_dGVzdF9jcHVfY2FwXzA_"><span class="b">test_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span><span class="f">)</span>
<a name="260" /><span class="Maybe">     260:</span> 
<a name="261" /><span class="Maybe">     261:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_dGhpc19jcHVfaGFzXzA_"><span class="b">this_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>                        \
<a name="262" /><span class="Maybe">     262:</span>     <span class="f">(</span><span class="b">__builtin_constant_p</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">&amp;&amp;</span> <a href="cpu.c_macros_ref.html#_UkVRVUlSRURfTUFTS19CSVRfU0VUXzA_"><span class="b">REQUIRED_MASK_BIT_SET</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">?</span> <span class="c">1</span> <span class="f">:</span>     \
<a name="263" /><span class="Maybe">     263:</span>      <a href="cpu.c_macros_noref.html#_eDg2X3RoaXNfY3B1X3Rlc3RfYml0XzA_"><span class="b">x86_this_cpu_test_bit</span></a><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="f">&amp;</span><span class="b">cpu_info</span><span class="f">.</span><span class="b">x86_capability</span><span class="f">)</span><span class="f">)</span>
<a name="264" /><span class="Maybe">     264:</span> 
<a name="265" /><span class="Maybe">     265:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_Y3B1X2hhc18w"><span class="b">cpu_has</span></a><span class="f">(</span><span class="f">&amp;</span><span class="b">boot_cpu_data</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>
<a name="266" /><span class="Maybe">     266:</span> 
<a name="267" /><span class="Maybe">     267:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0X2NwdV9jYXBfMA__"><span class="b">set_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>    <span class="b">set_bit</span><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="f">(</span><span class="f">(</span><span class="b">c</span><span class="f">)</span><span class="f">-&gt;</span><span class="b">x86_capability</span><span class="f">)</span><span class="f">)</span>
<a name="268" /><span class="Maybe">     268:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y2xlYXJfY3B1X2NhcF8w"><span class="b">clear_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>    <span class="b">clear_bit</span><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="f">(</span><span class="f">(</span><span class="b">c</span><span class="f">)</span><span class="f">-&gt;</span><span class="b">x86_capability</span><span class="f">)</span><span class="f">)</span>
<a name="269" /><span class="Maybe">     269:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0dXBfY2xlYXJfY3B1X2NhcF8w"><span class="b">setup_clear_cpu_cap</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="m">do</span> <span class="f">{</span> \
<a name="270" /><span class="Maybe">     270:</span>     <a href="cpu.c_macros_noref.html#_Y2xlYXJfY3B1X2NhcF8w"><span class="b">clear_cpu_cap</span></a><span class="f">(</span><span class="f">&amp;</span><span class="b">boot_cpu_data</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span><span class="f">;</span>    \
<a name="271" /><span class="Maybe">     271:</span>     <span class="b">set_bit</span><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="b">cpu_caps_cleared</span><span class="f">)</span><span class="f">;</span> \
<a name="272" /><span class="Maybe">     272:</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="273" /><span class="Maybe">     273:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0dXBfZm9yY2VfY3B1X2NhcF8w"><span class="b">setup_force_cpu_cap</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="m">do</span> <span class="f">{</span> \
<a name="274" /><span class="Maybe">     274:</span>     <a href="cpu.c_macros_noref.html#_c2V0X2NwdV9jYXBfMA__"><span class="b">set_cpu_cap</span></a><span class="f">(</span><span class="f">&amp;</span><span class="b">boot_cpu_data</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span><span class="f">;</span>    \
<a name="275" /><span class="Maybe">     275:</span>     <span class="b">set_bit</span><span class="f">(</span><span class="b">bit</span><span class="f">,</span> <span class="f">(</span><span class="m">unsigned</span> <span class="m">long</span> <span class="f">*</span><span class="f">)</span><span class="b">cpu_caps_set</span><span class="f">)</span><span class="f">;</span>    \
<a name="276" /><span class="Maybe">     276:</span> <span class="f">}</span> <span class="m">while</span> <span class="f">(</span><span class="c">0</span><span class="f">)</span>
<a name="277" /><span class="Maybe">     277:</span> 
<a name="278" /><span class="Maybe">     278:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19mcHVfMA__"><span class="b">cpu_has_fpu</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRlBVXzA_"><span class="b">X86_FEATURE_FPU</span></a><span class="f">)</span>
<a name="279" /><span class="Maybe">     279:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc192bWVfMQ__"><span class="b">cpu_has_vme</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVk1FXzA_"><span class="b">X86_FEATURE_VME</span></a><span class="f">)</span>
<a name="280" /><span class="Maybe">     280:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19kZV8w"><span class="b">cpu_has_de</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfREVfMA__"><span class="b">X86_FEATURE_DE</span></a><span class="f">)</span>
<a name="281" /><span class="Maybe">     281:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wc2VfMA__"><span class="b">cpu_has_pse</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUFNFXzA_"><span class="b">X86_FEATURE_PSE</span></a><span class="f">)</span>
<a name="282" /><span class="Maybe">     282:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc190c2NfMA__"><span class="b">cpu_has_tsc</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVFNDXzA_"><span class="b">X86_FEATURE_TSC</span></a><span class="f">)</span>
<a name="283" /><span class="Maybe">     283:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wYWVfMQ__"><span class="b">cpu_has_pae</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUEFFXzA_"><span class="b">X86_FEATURE_PAE</span></a><span class="f">)</span>
<a name="284" /><span class="Maybe">     284:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wZ2VfMA__"><span class="b">cpu_has_pge</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfUEdFXzA_"><span class="b">X86_FEATURE_PGE</span></a><span class="f">)</span>
<a name="285" /><span class="Maybe">     285:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hcGljXzA_"><span class="b">cpu_has_apic</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVBJQ18w"><span class="b">X86_FEATURE_APIC</span></a><span class="f">)</span>
<a name="286" /><span class="Maybe">     286:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19zZXBfMA__"><span class="b">cpu_has_sep</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU0VQXzA_"><span class="b">X86_FEATURE_SEP</span></a><span class="f">)</span>
<a name="287" /><span class="Maybe">     287:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19tdHJyXzA_"><span class="b">cpu_has_mtrr</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTVRSUl8w"><span class="b">X86_FEATURE_MTRR</span></a><span class="f">)</span>
<a name="288" /><span class="Maybe">     288:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19tbXhfMA__"><span class="b">cpu_has_mmx</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTU1YXzA_"><span class="b">X86_FEATURE_MMX</span></a><span class="f">)</span>
<a name="289" /><span class="Maybe">     289:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19meHNyXzA_"><span class="b">cpu_has_fxsr</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfRlhTUl8w"><span class="b">X86_FEATURE_FXSR</span></a><span class="f">)</span>
<a name="290" /><span class="Maybe">     290:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194bW1fMA__"><span class="b">cpu_has_xmm</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NXzA_"><span class="b">X86_FEATURE_XMM</span></a><span class="f">)</span>
<a name="291" /><span class="Maybe">     291:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194bW0yXzA_"><span class="b">cpu_has_xmm2</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWE1NMl8w"><span class="b">X86_FEATURE_XMM2</span></a><span class="f">)</span>
<a name="292" /><span class="Maybe">     292:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194bW0zXzA_"><span class="b">cpu_has_xmm3</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NM18w"><span class="b">X86_FEATURE_XMM3</span></a><span class="f">)</span>
<a name="293" /><span class="Maybe">     293:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19zc3NlM18w"><span class="b">cpu_has_ssse3</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfU1NTRTNfMA__"><span class="b">X86_FEATURE_SSSE3</span></a><span class="f">)</span>
<a name="294" /><span class="Maybe">     294:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hZXNfMA__"><span class="b">cpu_has_aes</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUVTXzA_"><span class="b">X86_FEATURE_AES</span></a><span class="f">)</span>
<a name="295" /><span class="Maybe">     295:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hdnhfMA__"><span class="b">cpu_has_avx</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVZYXzA_"><span class="b">X86_FEATURE_AVX</span></a><span class="f">)</span>
<a name="296" /><span class="Maybe">     296:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hdngyXzA_"><span class="b">cpu_has_avx2</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVZYMl8w"><span class="b">X86_FEATURE_AVX2</span></a><span class="f">)</span>
<a name="297" /><span class="Maybe">     297:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_Y3B1X2hhc19odF8w"><span class="b">cpu_has_ht</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfSFRfMA__"><span class="b">X86_FEATURE_HT</span></a><span class="f">)</span>
<a name="298" /><span class="Maybe">     298:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19tcF8x"><span class="b">cpu_has_mp</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTVBfMA__"><span class="b">X86_FEATURE_MP</span></a><span class="f">)</span>
<a name="299" /><span class="Maybe">     299:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19ueF8w"><span class="b">cpu_has_nx</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfTlhfMA__"><span class="b">X86_FEATURE_NX</span></a><span class="f">)</span>
<a name="300" /><span class="Maybe">     300:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19rNl9tdHJyXzE_"><span class="b">cpu_has_k6_mtrr</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSzZfTVRSUl8w"><span class="b">X86_FEATURE_K6_MTRR</span></a><span class="f">)</span>
<a name="301" /><span class="Maybe">     301:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jeXJpeF9hcnJfMQ__"><span class="b">cpu_has_cyrix_arr</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1lSSVhfQVJSXzA_"><span class="b">X86_FEATURE_CYRIX_ARR</span></a><span class="f">)</span>
<a name="302" /><span class="Maybe">     302:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jZW50YXVyX21jcl8x"><span class="b">cpu_has_centaur_mcr</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0VOVEFVUl9NQ1JfMA__"><span class="b">X86_FEATURE_CENTAUR_MCR</span></a><span class="f">)</span>
<a name="303" /><span class="Maybe">     303:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194c3RvcmVfMA__"><span class="b">cpu_has_xstore</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNUT1JFXzA_"><span class="b">X86_FEATURE_XSTORE</span></a><span class="f">)</span>
<a name="304" /><span class="Maybe">     304:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194c3RvcmVfZW5hYmxlZF8w"><span class="b">cpu_has_xstore_enabled</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNUT1JFX0VOXzA_"><span class="b">X86_FEATURE_XSTORE_EN</span></a><span class="f">)</span>
<a name="305" /><span class="Maybe">     305:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194Y3J5cHRfMA__"><span class="b">cpu_has_xcrypt</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWENSWVBUXzA_"><span class="b">X86_FEATURE_XCRYPT</span></a><span class="f">)</span>
<a name="306" /><span class="Maybe">     306:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194Y3J5cHRfZW5hYmxlZF8w"><span class="b">cpu_has_xcrypt_enabled</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWENSWVBUX0VOXzA_"><span class="b">X86_FEATURE_XCRYPT_EN</span></a><span class="f">)</span>
<a name="307" /><span class="Maybe">     307:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hY2UyXzA_"><span class="b">cpu_has_ace2</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUNFMl8w"><span class="b">X86_FEATURE_ACE2</span></a><span class="f">)</span>
<a name="308" /><span class="Maybe">     308:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hY2UyX2VuYWJsZWRfMA__"><span class="b">cpu_has_ace2_enabled</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQUNFMl9FTl8w"><span class="b">X86_FEATURE_ACE2_EN</span></a><span class="f">)</span>
<a name="309" /><span class="Maybe">     309:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19waGVfMA__"><span class="b">cpu_has_phe</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEhFXzA_"><span class="b">X86_FEATURE_PHE</span></a><span class="f">)</span>
<a name="310" /><span class="Maybe">     310:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19waGVfZW5hYmxlZF8w"><span class="b">cpu_has_phe_enabled</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEhFX0VOXzA_"><span class="b">X86_FEATURE_PHE_EN</span></a><span class="f">)</span>
<a name="311" /><span class="Maybe">     311:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wbW1fMA__"><span class="b">cpu_has_pmm</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUE1NXzA_"><span class="b">X86_FEATURE_PMM</span></a><span class="f">)</span>
<a name="312" /><span class="Maybe">     312:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wbW1fZW5hYmxlZF8w"><span class="b">cpu_has_pmm_enabled</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUE1NX0VOXzA_"><span class="b">X86_FEATURE_PMM_EN</span></a><span class="f">)</span>
<a name="313" /><span class="Maybe">     313:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19kc18w"><span class="b">cpu_has_ds</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRFNfMA__"><span class="b">X86_FEATURE_DS</span></a><span class="f">)</span>
<a name="314" /><span class="Maybe">     314:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wZWJzXzA_"><span class="b">cpu_has_pebs</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVCU18w"><span class="b">X86_FEATURE_PEBS</span></a><span class="f">)</span>
<a name="315" /><span class="Maybe">     315:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jbGZsdXNoXzA_"><span class="b">cpu_has_clflush</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ0xGTFNIXzA_"><span class="b">X86_FEATURE_CLFLSH</span></a><span class="f">)</span>
<a name="316" /><span class="Maybe">     316:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19idHNfMA__"><span class="b">cpu_has_bts</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQlRTXzA_"><span class="b">X86_FEATURE_BTS</span></a><span class="f">)</span>
<a name="317" /><span class="Maybe">     317:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19nYnBhZ2VzXzA_"><span class="b">cpu_has_gbpages</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfR0JQQUdFU18w"><span class="b">X86_FEATURE_GBPAGES</span></a><span class="f">)</span>
<a name="318" /><span class="Maybe">     318:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19hcmNoX3BlcmZtb25fMA__"><span class="b">cpu_has_arch_perfmon</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQVJDSF9QRVJGTU9OXzA_"><span class="b">X86_FEATURE_ARCH_PERFMON</span></a><span class="f">)</span>
<a name="319" /><span class="Maybe">     319:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wYXRfMA__"><span class="b">cpu_has_pat</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEFUXzA_"><span class="b">X86_FEATURE_PAT</span></a><span class="f">)</span>
<a name="320" /><span class="Maybe">     320:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194bW00XzFfMA__"><span class="b">cpu_has_xmm4_1</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NNF8xXzA_"><span class="b">X86_FEATURE_XMM4_1</span></a><span class="f">)</span>
<a name="321" /><span class="Maybe">     321:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194bW00XzJfMA__"><span class="b">cpu_has_xmm4_2</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWE1NNF8yXzA_"><span class="b">X86_FEATURE_XMM4_2</span></a><span class="f">)</span>
<a name="322" /><span class="Maybe">     322:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_Y3B1X2hhc194MmFwaWNfMA__"><span class="b">cpu_has_x2apic</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfWDJBUElDXzA_"><span class="b">X86_FEATURE_X2APIC</span></a><span class="f">)</span>
<a name="323" /><span class="Maybe">     323:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194c2F2ZV8w"><span class="b">cpu_has_xsave</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNBVkVfMA__"><span class="b">X86_FEATURE_XSAVE</span></a><span class="f">)</span>
<a name="324" /><span class="Maybe">     324:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc194c2F2ZW9wdF8w"><span class="b">cpu_has_xsaveopt</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfWFNBVkVPUFRfMA__"><span class="b">X86_FEATURE_XSAVEOPT</span></a><span class="f">)</span>
<a name="325" /><span class="Maybe">     325:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19vc3hzYXZlXzA_"><span class="b">cpu_has_osxsave</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfT1NYU0FWRV8w"><span class="b">X86_FEATURE_OSXSAVE</span></a><span class="f">)</span>
<a name="326" /><span class="Maybe">     326:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19oeXBlcnZpc29yXzA_"><span class="b">cpu_has_hypervisor</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfSFlQRVJWSVNPUl8w"><span class="b">X86_FEATURE_HYPERVISOR</span></a><span class="f">)</span>
<a name="327" /><span class="Maybe">     327:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wY2xtdWxxZHFfMA__"><span class="b">cpu_has_pclmulqdq</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUENMTVVMUURRXzA_"><span class="b">X86_FEATURE_PCLMULQDQ</span></a><span class="f">)</span>
<a name="328" /><span class="Maybe">     328:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wZXJmY3RyX2NvcmVfMA__"><span class="b">cpu_has_perfctr_core</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9DT1JFXzA_"><span class="b">X86_FEATURE_PERFCTR_CORE</span></a><span class="f">)</span>
<a name="329" /><span class="Maybe">     329:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wZXJmY3RyX25iXzA_"><span class="b">cpu_has_perfctr_nb</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9OQl8w"><span class="b">X86_FEATURE_PERFCTR_NB</span></a><span class="f">)</span>
<a name="330" /><span class="Maybe">     330:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wZXJmY3RyX2wyXzA_"><span class="b">cpu_has_perfctr_l2</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfUEVSRkNUUl9MMl8w"><span class="b">X86_FEATURE_PERFCTR_L2</span></a><span class="f">)</span>
<a name="331" /><span class="Maybe">     331:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jeDhfMA__"><span class="b">cpu_has_cx8</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQ1g4XzA_"><span class="b">X86_FEATURE_CX8</span></a><span class="f">)</span>
<a name="332" /><span class="Maybe">     332:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jeDE2XzA_"><span class="b">cpu_has_cx16</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfQ1gxNl8w"><span class="b">X86_FEATURE_CX16</span></a><span class="f">)</span>
<a name="333" /><span class="Maybe">     333:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19lYWdlcl9mcHVfMA__"><span class="b">cpu_has_eager_fpu</span></a>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfRUFHRVJfRlBVXzA_"><span class="b">X86_FEATURE_EAGER_FPU</span></a><span class="f">)</span>
<a name="334" /><span class="Maybe">     334:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc190b3BvZXh0XzA_"><span class="b">cpu_has_topoext</span></a>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><a href="cpu.c_macros_noref.html#_WDg2X0ZFQVRVUkVfVE9QT0VYVF8w"><span class="b">X86_FEATURE_TOPOEXT</span></a><span class="f">)</span>
<a name="335" /><span class="Maybe">     335:</span> 
<a name="336" /><span class="Maybe">     336:</span> <span class="f">#</span><span class="n">ifdef</span> <a href="cpu.c_macros_ref.html#_Q09ORklHX1g4Nl82NF8w"><span class="b">CONFIG_X86_64</span></a>
<a name="337" /><span class="Maybe">     337:</span> 
<a name="338" /><span class="Maybe">     338:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc192bWVfMQ__"><span class="b">cpu_has_vme</span></a>
<a name="339" /><span class="Maybe">     339:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc192bWVfMQ__"><span class="b">cpu_has_vme</span></a>        <span class="c">0</span>
<a name="340" /><span class="Maybe">     340:</span> 
<a name="341" /><span class="Maybe">     341:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wYWVfMQ__"><span class="b">cpu_has_pae</span></a>
<a name="342" /><span class="Maybe">     342:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19wYWVfMQ__"><span class="b">cpu_has_pae</span></a>        <span class="b">___BUG___</span>
<a name="343" /><span class="Maybe">     343:</span> 
<a name="344" /><span class="Maybe">     344:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19tcF8x"><span class="b">cpu_has_mp</span></a>
<a name="345" /><span class="Maybe">     345:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19tcF8x"><span class="b">cpu_has_mp</span></a>        <span class="c">1</span>
<a name="346" /><span class="Maybe">     346:</span> 
<a name="347" /><span class="Maybe">     347:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19rNl9tdHJyXzE_"><span class="b">cpu_has_k6_mtrr</span></a>
<a name="348" /><span class="Maybe">     348:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19rNl9tdHJyXzE_"><span class="b">cpu_has_k6_mtrr</span></a>        <span class="c">0</span>
<a name="349" /><span class="Maybe">     349:</span> 
<a name="350" /><span class="Maybe">     350:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jeXJpeF9hcnJfMQ__"><span class="b">cpu_has_cyrix_arr</span></a>
<a name="351" /><span class="Maybe">     351:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jeXJpeF9hcnJfMQ__"><span class="b">cpu_has_cyrix_arr</span></a>    <span class="c">0</span>
<a name="352" /><span class="Maybe">     352:</span> 
<a name="353" /><span class="Maybe">     353:</span> <span class="f">#</span><span class="n">undef</span>  <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jZW50YXVyX21jcl8x"><span class="b">cpu_has_centaur_mcr</span></a>
<a name="354" /><span class="Maybe">     354:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19jZW50YXVyX21jcl8x"><span class="b">cpu_has_centaur_mcr</span></a>    <span class="c">0</span>
<a name="355" /><span class="Maybe">     355:</span> 
<a name="356" /><span class="Maybe">     356:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* CONFIG_X86_64 */</span>
<a name="357" /><span class="Maybe">     357:</span> 
<a name="358" /><span class="Maybe">     358:</span> <span class="f">#</span><span class="n">if</span> <a href="cpu.c_macros_ref.html#_X19HTlVDX19fMA__"><span class="b">__GNUC__</span></a> <span class="f">&gt;=</span> <span class="c">4</span>
<a name="359" /><span class="Maybe">     359:</span> <span class="m">extern</span> <span class="m">void</span> <span class="b">warn_pre_alternatives</span><span class="f">(</span><span class="m">void</span><span class="f">)</span><span class="f">;</span>
<a name="360" /><span class="Maybe">     360:</span> <span class="m">extern</span> <span class="m">bool</span> <span class="b">__static_cpu_has_safe</span><span class="f">(</span><span class="b">u16</span> <span class="b">bit</span><span class="f">)</span><span class="f">;</span>
<a name="361" /><span class="Maybe">     361:</span> 
<a name="362" /><span class="Maybe">     362:</span> <span class="k">/*</span>
<a name="363" /><span class="Maybe">     363:</span> <span class="k"> * Static testing of CPU features.  Used the same as boot_cpu_has().</span>
<a name="364" /><span class="Maybe">     364:</span> <span class="k"> * These are only valid after alternatives have run, but will statically</span>
<a name="365" /><span class="Maybe">     365:</span> <span class="k"> * patch the target code for additional performance.</span>
<a name="366" /><span class="Maybe">     366:</span> <span class="k"> */</span>
<a name="367" /><span class="Maybe">     367:</span> <span class="m">static</span> <a href="cpu.c_macros_ref.html#_X19hbHdheXNfaW5saW5lXzA_"><span class="b">__always_inline</span></a> <a href="cpu.c_macros_ref.html#_X19wdXJlXzA_"><span class="b">__pure</span></a> <span class="m">bool</span> <span class="b">__static_cpu_has</span><span class="f">(</span><span class="b">u16</span> <span class="b">bit</span><span class="f">)</span>
<a name="368" /><span class="Maybe">     368:</span> <span class="f">{</span>
<a name="369" /><span class="False">     369:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CC_HAVE_ASM_GOTO</span>
<a name="370" /><span class="False">     370:</span> 
<a name="371" /><span class="False">     371:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_DEBUG_STATIC_CPU_HAS</span>
<a name="372" /><span class="False">     372:</span> 
<a name="373" /><span class="False">     373:</span>         <span class="k">/*</span>
<a name="374" /><span class="False">     374:</span> <span class="k">         * Catch too early usage of this before alternatives</span>
<a name="375" /><span class="False">     375:</span> <span class="k">         * have run.</span>
<a name="376" /><span class="False">     376:</span> <span class="k">         */</span>
<a name="377" /><span class="False">     377:</span>         <a href="cpu.c_macros_noref.html#_YXNtX3ZvbGF0aWxlX2dvdG9fMA__"><span class="b">asm_volatile_goto</span></a><span class="f">(</span><span class="e">&quot;1: jmp %l[t_warn]\n&quot;</span>
<a name="378" /><span class="False">     378:</span>              <span class="e">&quot;2:\n&quot;</span>
<a name="379" /><span class="False">     379:</span>              <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="380" /><span class="False">     380:</span>              <span class="e">&quot; .long 1b - .\n&quot;</span>
<a name="381" /><span class="False">     381:</span>              <span class="e">&quot; .long 0\n&quot;</span>        <span class="k">/* no replacement */</span>
<a name="382" /><span class="False">     382:</span>              <span class="e">&quot; .word %P0\n&quot;</span>        <span class="k">/* 1: do replace */</span>
<a name="383" /><span class="False">     383:</span>              <span class="e">&quot; .byte 2b - 1b\n&quot;</span>    <span class="k">/* source len */</span>
<a name="384" /><span class="False">     384:</span>              <span class="e">&quot; .byte 0\n&quot;</span>        <span class="k">/* replacement len */</span>
<a name="385" /><span class="False">     385:</span>              <span class="e">&quot;.previous\n&quot;</span>
<a name="386" /><span class="False">     386:</span>              <span class="k">/* skipping size check since replacement size = 0 */</span>
<a name="387" /><span class="False">     387:</span>              <span class="f">:</span> <span class="f">:</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQUxXQVlTXzA_"><span class="b">X86_FEATURE_ALWAYS</span></a><span class="f">)</span> <span class="f">:</span> <span class="f">:</span> <span class="b">t_warn</span><span class="f">)</span><span class="f">;</span>
<a name="388" /><span class="False">     388:</span> 
<a name="389" /><span class="False">     389:</span> <span class="f">#</span><span class="n">endif</span>
<a name="390" /><span class="False">     390:</span> 
<a name="391" /><span class="False">     391:</span>         <a href="cpu.c_macros_noref.html#_YXNtX3ZvbGF0aWxlX2dvdG9fMA__"><span class="b">asm_volatile_goto</span></a><span class="f">(</span><span class="e">&quot;1: jmp %l[t_no]\n&quot;</span>
<a name="392" /><span class="False">     392:</span>              <span class="e">&quot;2:\n&quot;</span>
<a name="393" /><span class="False">     393:</span>              <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="394" /><span class="False">     394:</span>              <span class="e">&quot; .long 1b - .\n&quot;</span>
<a name="395" /><span class="False">     395:</span>              <span class="e">&quot; .long 0\n&quot;</span>        <span class="k">/* no replacement */</span>
<a name="396" /><span class="False">     396:</span>              <span class="e">&quot; .word %P0\n&quot;</span>        <span class="k">/* feature bit */</span>
<a name="397" /><span class="False">     397:</span>              <span class="e">&quot; .byte 2b - 1b\n&quot;</span>    <span class="k">/* source len */</span>
<a name="398" /><span class="False">     398:</span>              <span class="e">&quot; .byte 0\n&quot;</span>        <span class="k">/* replacement len */</span>
<a name="399" /><span class="False">     399:</span>              <span class="e">&quot;.previous\n&quot;</span>
<a name="400" /><span class="False">     400:</span>              <span class="k">/* skipping size check since replacement size = 0 */</span>
<a name="401" /><span class="False">     401:</span>              <span class="f">:</span> <span class="f">:</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">:</span> <span class="f">:</span> <span class="b">t_no</span><span class="f">)</span><span class="f">;</span>
<a name="402" /><span class="False">     402:</span>         <span class="m">return</span> <span class="m">true</span><span class="f">;</span>
<a name="403" /><span class="False">     403:</span>     <span class="b">t_no</span><span class="f">:</span>
<a name="404" /><span class="False">     404:</span>         <span class="m">return</span> <span class="m">false</span><span class="f">;</span>
<a name="405" /><span class="False">     405:</span> 
<a name="406" /><span class="False">     406:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_DEBUG_STATIC_CPU_HAS</span>
<a name="407" /><span class="False">     407:</span>     <span class="b">t_warn</span><span class="f">:</span>
<a name="408" /><span class="False">     408:</span>         <span class="b">warn_pre_alternatives</span><span class="f">(</span><span class="f">)</span><span class="f">;</span>
<a name="409" /><span class="False">     409:</span>         <span class="m">return</span> <span class="m">false</span><span class="f">;</span>
<a name="410" /><span class="False">     410:</span> <span class="f">#</span><span class="n">endif</span>
<a name="411" /><span class="False">     411:</span> 
<a name="412" /><span class="Maybe">     412:</span> <span class="f">#</span><span class="n">else</span> <span class="k">/* CC_HAVE_ASM_GOTO */</span>
<a name="413" /><span class="Maybe">     413:</span> 
<a name="414" /><span class="Maybe">     414:</span>         <span class="b">u8</span> <span class="b">flag</span><span class="f">;</span>
<a name="415" /><span class="Maybe">     415:</span>         <span class="k">/* Open-coded due to __stringify() in ALTERNATIVE() */</span>
<a name="416" /><span class="Maybe">     416:</span>         <span class="m">asm</span> <span class="m">volatile</span><span class="f">(</span><span class="e">&quot;1: movb $0,%0\n&quot;</span>
<a name="417" /><span class="Maybe">     417:</span>                  <span class="e">&quot;2:\n&quot;</span>
<a name="418" /><span class="Maybe">     418:</span>                  <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="419" /><span class="Maybe">     419:</span>                  <span class="e">&quot; .long 1b - .\n&quot;</span>
<a name="420" /><span class="Maybe">     420:</span>                  <span class="e">&quot; .long 3f - .\n&quot;</span>
<a name="421" /><span class="Maybe">     421:</span>                  <span class="e">&quot; .word %P1\n&quot;</span>        <span class="k">/* feature bit */</span>
<a name="422" /><span class="Maybe">     422:</span>                  <span class="e">&quot; .byte 2b - 1b\n&quot;</span>        <span class="k">/* source len */</span>
<a name="423" /><span class="Maybe">     423:</span>                  <span class="e">&quot; .byte 4f - 3f\n&quot;</span>        <span class="k">/* replacement len */</span>
<a name="424" /><span class="Maybe">     424:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="425" /><span class="Maybe">     425:</span>                  <span class="e">&quot;.section .discard,\&quot;aw\&quot;,@progbits\n&quot;</span>
<a name="426" /><span class="Maybe">     426:</span>                  <span class="e">&quot; .byte 0xff + (4f-3f) - (2b-1b)\n&quot;</span> <span class="k">/* size check */</span>
<a name="427" /><span class="Maybe">     427:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="428" /><span class="Maybe">     428:</span>                  <span class="e">&quot;.section .altinstr_replacement,\&quot;ax\&quot;\n&quot;</span>
<a name="429" /><span class="Maybe">     429:</span>                  <span class="e">&quot;3: movb $1,%0\n&quot;</span>
<a name="430" /><span class="Maybe">     430:</span>                  <span class="e">&quot;4:\n&quot;</span>
<a name="431" /><span class="Maybe">     431:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="432" /><span class="Maybe">     432:</span>                  <span class="f">:</span> <span class="e">&quot;=qm&quot;</span> <span class="f">(</span><span class="b">flag</span><span class="f">)</span> <span class="f">:</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span><span class="f">;</span>
<a name="433" /><span class="Maybe">     433:</span>         <span class="m">return</span> <span class="b">flag</span><span class="f">;</span>
<a name="434" /><span class="Maybe">     434:</span> 
<a name="435" /><span class="Maybe">     435:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* CC_HAVE_ASM_GOTO */</span>
<a name="436" /><span class="Maybe">     436:</span> <span class="f">}</span>
<a name="437" /><span class="Maybe">     437:</span> 
<a name="438" /><span class="Maybe">     438:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfMA__"><span class="b">static_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>                    \
<a name="439" /><span class="Maybe">     439:</span> <span class="f">(</span>                                \
<a name="440" /><span class="Maybe">     440:</span>     <span class="b">__builtin_constant_p</span><span class="f">(</span><a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span> <span class="f">?</span>        \
<a name="441" /><span class="Maybe">     441:</span>         <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">:</span>                \
<a name="442" /><span class="Maybe">     442:</span>     <span class="b">__builtin_constant_p</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">?</span>                \
<a name="443" /><span class="Maybe">     443:</span>         <span class="b">__static_cpu_has</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">:</span>                \
<a name="444" /><span class="Maybe">     444:</span>         <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>                \
<a name="445" /><span class="Maybe">     445:</span> <span class="f">)</span>
<a name="446" /><span class="Maybe">     446:</span> 
<a name="447" /><span class="Maybe">     447:</span> <span class="m">static</span> <a href="cpu.c_macros_ref.html#_X19hbHdheXNfaW5saW5lXzA_"><span class="b">__always_inline</span></a> <a href="cpu.c_macros_ref.html#_X19wdXJlXzA_"><span class="b">__pure</span></a> <span class="m">bool</span> <span class="b">_static_cpu_has_safe</span><span class="f">(</span><span class="b">u16</span> <span class="b">bit</span><span class="f">)</span>
<a name="448" /><span class="Maybe">     448:</span> <span class="f">{</span>
<a name="449" /><span class="False">     449:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CC_HAVE_ASM_GOTO</span>
<a name="450" /><span class="False">     450:</span> <span class="k">/*</span>
<a name="451" /><span class="False">     451:</span> <span class="k"> * We need to spell the jumps to the compiler because, depending on the offset,</span>
<a name="452" /><span class="False">     452:</span> <span class="k"> * the replacement jump can be bigger than the original jump, and this we cannot</span>
<a name="453" /><span class="False">     453:</span> <span class="k"> * have. Thus, we force the jump to the widest, 4-byte, signed relative</span>
<a name="454" /><span class="False">     454:</span> <span class="k"> * offset even though the last would often fit in less bytes.</span>
<a name="455" /><span class="False">     455:</span> <span class="k"> */</span>
<a name="456" /><span class="False">     456:</span>         <a href="cpu.c_macros_noref.html#_YXNtX3ZvbGF0aWxlX2dvdG9fMA__"><span class="b">asm_volatile_goto</span></a><span class="f">(</span><span class="e">&quot;1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n&quot;</span>
<a name="457" /><span class="False">     457:</span>              <span class="e">&quot;2:\n&quot;</span>
<a name="458" /><span class="False">     458:</span>              <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="459" /><span class="False">     459:</span>              <span class="e">&quot; .long 1b - .\n&quot;</span>        <span class="k">/* src offset */</span>
<a name="460" /><span class="False">     460:</span>              <span class="e">&quot; .long 3f - .\n&quot;</span>        <span class="k">/* repl offset */</span>
<a name="461" /><span class="False">     461:</span>              <span class="e">&quot; .word %P1\n&quot;</span>            <span class="k">/* always replace */</span>
<a name="462" /><span class="False">     462:</span>              <span class="e">&quot; .byte 2b - 1b\n&quot;</span>        <span class="k">/* src len */</span>
<a name="463" /><span class="False">     463:</span>              <span class="e">&quot; .byte 4f - 3f\n&quot;</span>        <span class="k">/* repl len */</span>
<a name="464" /><span class="False">     464:</span>              <span class="e">&quot;.previous\n&quot;</span>
<a name="465" /><span class="False">     465:</span>              <span class="e">&quot;.section .altinstr_replacement,\&quot;ax\&quot;\n&quot;</span>
<a name="466" /><span class="False">     466:</span>              <span class="e">&quot;3: .byte 0xe9\n .long %l[t_no] - 2b\n&quot;</span>
<a name="467" /><span class="False">     467:</span>              <span class="e">&quot;4:\n&quot;</span>
<a name="468" /><span class="False">     468:</span>              <span class="e">&quot;.previous\n&quot;</span>
<a name="469" /><span class="False">     469:</span>              <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="470" /><span class="False">     470:</span>              <span class="e">&quot; .long 1b - .\n&quot;</span>        <span class="k">/* src offset */</span>
<a name="471" /><span class="False">     471:</span>              <span class="e">&quot; .long 0\n&quot;</span>            <span class="k">/* no replacement */</span>
<a name="472" /><span class="False">     472:</span>              <span class="e">&quot; .word %P0\n&quot;</span>            <span class="k">/* feature bit */</span>
<a name="473" /><span class="False">     473:</span>              <span class="e">&quot; .byte 2b - 1b\n&quot;</span>        <span class="k">/* src len */</span>
<a name="474" /><span class="False">     474:</span>              <span class="e">&quot; .byte 0\n&quot;</span>            <span class="k">/* repl len */</span>
<a name="475" /><span class="False">     475:</span>              <span class="e">&quot;.previous\n&quot;</span>
<a name="476" /><span class="False">     476:</span>              <span class="f">:</span> <span class="f">:</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">,</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQUxXQVlTXzA_"><span class="b">X86_FEATURE_ALWAYS</span></a><span class="f">)</span>
<a name="477" /><span class="False">     477:</span>              <span class="f">:</span> <span class="f">:</span> <span class="b">t_dynamic</span><span class="f">,</span> <span class="b">t_no</span><span class="f">)</span><span class="f">;</span>
<a name="478" /><span class="False">     478:</span>         <span class="m">return</span> <span class="m">true</span><span class="f">;</span>
<a name="479" /><span class="False">     479:</span>     <span class="b">t_no</span><span class="f">:</span>
<a name="480" /><span class="False">     480:</span>         <span class="m">return</span> <span class="m">false</span><span class="f">;</span>
<a name="481" /><span class="False">     481:</span>     <span class="b">t_dynamic</span><span class="f">:</span>
<a name="482" /><span class="False">     482:</span>         <span class="m">return</span> <span class="b">__static_cpu_has_safe</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">;</span>
<a name="483" /><span class="Maybe">     483:</span> <span class="f">#</span><span class="n">else</span>
<a name="484" /><span class="Maybe">     484:</span>         <span class="b">u8</span> <span class="b">flag</span><span class="f">;</span>
<a name="485" /><span class="Maybe">     485:</span>         <span class="k">/* Open-coded due to __stringify() in ALTERNATIVE() */</span>
<a name="486" /><span class="Maybe">     486:</span>         <span class="m">asm</span> <span class="m">volatile</span><span class="f">(</span><span class="e">&quot;1: movb $2,%0\n&quot;</span>
<a name="487" /><span class="Maybe">     487:</span>                  <span class="e">&quot;2:\n&quot;</span>
<a name="488" /><span class="Maybe">     488:</span>                  <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="489" /><span class="Maybe">     489:</span>                  <span class="e">&quot; .long 1b - .\n&quot;</span>        <span class="k">/* src offset */</span>
<a name="490" /><span class="Maybe">     490:</span>                  <span class="e">&quot; .long 3f - .\n&quot;</span>        <span class="k">/* repl offset */</span>
<a name="491" /><span class="Maybe">     491:</span>                  <span class="e">&quot; .word %P2\n&quot;</span>        <span class="k">/* always replace */</span>
<a name="492" /><span class="Maybe">     492:</span>                  <span class="e">&quot; .byte 2b - 1b\n&quot;</span>        <span class="k">/* source len */</span>
<a name="493" /><span class="Maybe">     493:</span>                  <span class="e">&quot; .byte 4f - 3f\n&quot;</span>        <span class="k">/* replacement len */</span>
<a name="494" /><span class="Maybe">     494:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="495" /><span class="Maybe">     495:</span>                  <span class="e">&quot;.section .discard,\&quot;aw\&quot;,@progbits\n&quot;</span>
<a name="496" /><span class="Maybe">     496:</span>                  <span class="e">&quot; .byte 0xff + (4f-3f) - (2b-1b)\n&quot;</span> <span class="k">/* size check */</span>
<a name="497" /><span class="Maybe">     497:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="498" /><span class="Maybe">     498:</span>                  <span class="e">&quot;.section .altinstr_replacement,\&quot;ax\&quot;\n&quot;</span>
<a name="499" /><span class="Maybe">     499:</span>                  <span class="e">&quot;3: movb $0,%0\n&quot;</span>
<a name="500" /><span class="Maybe">     500:</span>                  <span class="e">&quot;4:\n&quot;</span>
<a name="501" /><span class="Maybe">     501:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="502" /><span class="Maybe">     502:</span>                  <span class="e">&quot;.section .altinstructions,\&quot;a\&quot;\n&quot;</span>
<a name="503" /><span class="Maybe">     503:</span>                  <span class="e">&quot; .long 1b - .\n&quot;</span>        <span class="k">/* src offset */</span>
<a name="504" /><span class="Maybe">     504:</span>                  <span class="e">&quot; .long 5f - .\n&quot;</span>        <span class="k">/* repl offset */</span>
<a name="505" /><span class="Maybe">     505:</span>                  <span class="e">&quot; .word %P1\n&quot;</span>        <span class="k">/* feature bit */</span>
<a name="506" /><span class="Maybe">     506:</span>                  <span class="e">&quot; .byte 4b - 3b\n&quot;</span>        <span class="k">/* src len */</span>
<a name="507" /><span class="Maybe">     507:</span>                  <span class="e">&quot; .byte 6f - 5f\n&quot;</span>        <span class="k">/* repl len */</span>
<a name="508" /><span class="Maybe">     508:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="509" /><span class="Maybe">     509:</span>                  <span class="e">&quot;.section .discard,\&quot;aw\&quot;,@progbits\n&quot;</span>
<a name="510" /><span class="Maybe">     510:</span>                  <span class="e">&quot; .byte 0xff + (6f-5f) - (4b-3b)\n&quot;</span> <span class="k">/* size check */</span>
<a name="511" /><span class="Maybe">     511:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="512" /><span class="Maybe">     512:</span>                  <span class="e">&quot;.section .altinstr_replacement,\&quot;ax\&quot;\n&quot;</span>
<a name="513" /><span class="Maybe">     513:</span>                  <span class="e">&quot;5: movb $1,%0\n&quot;</span>
<a name="514" /><span class="Maybe">     514:</span>                  <span class="e">&quot;6:\n&quot;</span>
<a name="515" /><span class="Maybe">     515:</span>                  <span class="e">&quot;.previous\n&quot;</span>
<a name="516" /><span class="Maybe">     516:</span>                  <span class="f">:</span> <span class="e">&quot;=qm&quot;</span> <span class="f">(</span><span class="b">flag</span><span class="f">)</span>
<a name="517" /><span class="Maybe">     517:</span>                  <span class="f">:</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">,</span> <span class="e">&quot;i&quot;</span> <span class="f">(</span><a href="cpu.c_macros_ref.html#_WDg2X0ZFQVRVUkVfQUxXQVlTXzA_"><span class="b">X86_FEATURE_ALWAYS</span></a><span class="f">)</span><span class="f">)</span><span class="f">;</span>
<a name="518" /><span class="Maybe">     518:</span>         <span class="m">return</span> <span class="f">(</span><span class="b">flag</span> <span class="f">==</span> <span class="c">2</span> <span class="f">?</span> <span class="b">__static_cpu_has_safe</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">:</span> <span class="b">flag</span><span class="f">)</span><span class="f">;</span>
<a name="519" /><span class="Maybe">     519:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* CC_HAVE_ASM_GOTO */</span>
<a name="520" /><span class="Maybe">     520:</span> <span class="f">}</span>
<a name="521" /><span class="Maybe">     521:</span> 
<a name="522" /><span class="Maybe">     522:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfc2FmZV8w"><span class="b">static_cpu_has_safe</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>                \
<a name="523" /><span class="Maybe">     523:</span> <span class="f">(</span>                                \
<a name="524" /><span class="Maybe">     524:</span>     <span class="b">__builtin_constant_p</span><span class="f">(</span><a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span> <span class="f">?</span>        \
<a name="525" /><span class="Maybe">     525:</span>         <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span> <span class="f">:</span>                \
<a name="526" /><span class="Maybe">     526:</span>         <span class="b">_static_cpu_has_safe</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span>            \
<a name="527" /><span class="Maybe">     527:</span> <span class="f">)</span>
<a name="528" /><span class="False">     528:</span> <span class="f">#</span><span class="n">else</span>
<a name="529" /><span class="False">     529:</span> <span class="k">/*</span>
<a name="530" /><span class="False">     530:</span> <span class="k"> * gcc 3.x is too stupid to do the static test; fall back to dynamic.</span>
<a name="531" /><span class="False">     531:</span> <span class="k"> */</span>
<a name="532" /><span class="False">     532:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfMA__"><span class="b">static_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>        <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>
<a name="533" /><span class="False">     533:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfc2FmZV8w"><span class="b">static_cpu_has_safe</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_Ym9vdF9jcHVfaGFzXzA_"><span class="b">boot_cpu_has</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>
<a name="534" /><span class="Maybe">     534:</span> <span class="f">#</span><span class="n">endif</span>
<a name="535" /><span class="Maybe">     535:</span> 
<a name="536" /><span class="Maybe">     536:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19idWdfMA__"><span class="b">cpu_has_bug</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_ref.html#_Y3B1X2hhc18w"><span class="b">cpu_has</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span>
<a name="537" /><span class="Maybe">     537:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c2V0X2NwdV9idWdfMA__"><span class="b">set_cpu_bug</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_noref.html#_c2V0X2NwdV9jYXBfMA__"><span class="b">set_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span>
<a name="538" /><span class="Maybe">     538:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Y2xlYXJfY3B1X2J1Z18w"><span class="b">clear_cpu_bug</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_noref.html#_Y2xlYXJfY3B1X2NhcF8w"><span class="b">clear_cpu_cap</span></a><span class="f">(</span><span class="b">c</span><span class="f">,</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span><span class="f">;</span>
<a name="539" /><span class="Maybe">     539:</span> 
<a name="540" /><span class="Maybe">     540:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfYnVnXzA_"><span class="b">static_cpu_has_bug</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_noref.html#_c3RhdGljX2NwdV9oYXNfMA__"><span class="b">static_cpu_has</span></a><span class="f">(</span><span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span>
<a name="541" /><span class="Maybe">     541:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Ym9vdF9jcHVfaGFzX2J1Z18w"><span class="b">boot_cpu_has_bug</span></a><span class="f">(</span><span class="b">bit</span><span class="f">)</span>    <a href="cpu.c_macros_noref.html#_Y3B1X2hhc19idWdfMA__"><span class="b">cpu_has_bug</span></a><span class="f">(</span><span class="f">&amp;</span><span class="b">boot_cpu_data</span><span class="f">,</span> <span class="f">(</span><span class="b">bit</span><span class="f">)</span><span class="f">)</span>
<a name="542" /><span class="Maybe">     542:</span> 
<a name="543" /><span class="Maybe">     543:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* defined(__KERNEL__) &amp;&amp; !defined(__ASSEMBLY__) */</span>
<a name="544" /><span class="Maybe">     544:</span> 
<a name="545" /><span class="True">     545:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* _ASM_X86_CPUFEATURE_H */</span>
<a name="546" /><span class="True">     546:</span> </pre>
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